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LTC2634 Quad 12-/10-/8-Bit Rail-to-Rail DACs with 10ppm/C Reference FEATURES
n
DESCRIPTION
The LTC(R)2634 is a family of quad 12-, 10- and 8-bit voltage output DACs with an integrated, high accuracy, low drift 10ppm/C reference in 16-lead QFN and 10-lead MSOP packages. It has rail-to-rail output buffers and is guaranteed monotonic. The LTC2634-L has a full-scale output of 2.5V, and operates from a single 2.7V to 5.5V supply. The LTC2634-H has a full-scale output of 4.096V, and operates from a 4.5V to 5.5V supply. Each DAC can also operate with an external reference, which sets the full-scale output to the external reference voltage. These DACs communicate via an SPI/MICROWIRE compatible 3-wire serial interface which operates at clock rates up to 50MHz. Serial data output (SDO), a hardware clear (CLR), and an asynchronous DAC update (LDAC) capability are available in the QFN package. The LTC2634 incorporates a power-on reset circuit. Options are available for reset to zero-scale or reset to mid-scale in internal reference mode, or reset to mid-scale in external reference mode after power-up.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5396245, 5859606, 6891433, 6937178, 7414561.
n n n n n n n n n n
Integrated Precision Reference 2.5V Full-Scale 10ppm/C (LTC2634-L) 4.096V Full-Scale 10ppm/C (LTC2634-H) Maximum INL Error: 2.5 LSB (LTC2634-12) Low Noise: 0.75mVP-P 0.1Hz to 200KHz Guaranteed Monotonic over -40C to 125C Temperature Range Selectable Internal or External Reference 2.7V to 5.5V Supply Range (LTC2634-L) Ultralow Crosstalk Between DACs (2.4nV*s) Low Power: 0.6mA at 3V Power-On Reset to Zero-Scale/Mid-Scale Double Buffered Data Latches Tiny 16-Lead 3mm x 3mm QFN and 10-Lead MSOP Packages
APPLICATIONS
n n n n n
Mobile Communications Process Control and Industrial Automation Automatic Test Equipment Portable Equipment Automotive
BLOCK DIAGRAM
GND INTERNAL REFERENCE SWITCH VREF (REFLO) REGISTER REGISTER REGISTER REGISTER VOUTA VCC 2 DAC D VOUTD 1 VREF REGISTER REGISTER REGISTER REGISTER DAC B DAC C VOUTC INL (LSB) VCC = 3V INTERNAL REF REF
Integral Nonlinearity (LTC2634-LZ12)
DAC A
VREF VOUTB
0
CS/LD CONTROL LOGIC DECODE
SDI
SDI
-1
-2 SCK (LDAC) ( ) QFN PACKAGE ONLY 32-BIT SHIFT REGISTER POWER-ON RESET (CLR) (SDO)
2634 BD
0
1024
2048 CODE
3072
4095
2634 TA01
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LTC2634 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Supply Voltage (VCC) ................................... -0.3V to 6V CS/LD, SCK, SDI, LDAC, CLR, SDO, REFLO.. -0.3V to 6V VOUTA-VOUTD .................... -0.3V to Min (VCC + 0.3V, 6V) REF .................................. -0.3V to Min (VCC + 0.3V, 6V) Operating Temperature Range LTC2634C ................................................ 0C to 70C LTC2634I.............................................. -40C to 85C LTC2634H (Note 3) ............................ -40C to 125C Maximum Junction Temperature........................... 150C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) MSOP ............................................................... 300C
PIN CONFIGURATION
REFLO TOP VIEW GND VCC NC
16 15 14 13 VOUTA 1 VOUTB 2 LDAC 3 CS/LD 4 5 SCK 6 NC 7 SDO 8 SDI 17 12 VOUTD 11 VOUTC 10 REF 9 CLR VCC 1 VOUTA 2 VOUTB 3 CS/LD 4 SCK 5
TOP VIEW 10 9 8 7 6 GND VOUTD VOUTC REF SDI
11
MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 35C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
UD PACKAGE 16-LEAD (3mm 3mm) PLASTIC QFN TJMAX = 125C, JA = 68C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
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LTC2634 ORDER INFORMATION
LTC2634 C UD -L Z 12 #TR PBF LEAD FREE DESIGNATOR PBF = Lead Free TAPE AND REEL TR = 2,500-Piece Tape and Reel RESOLUTION 12 = 12-Bit 10 = 10-Bit 8 = 8-Bit POWER-ON RESET MI = Reset to Mid-Scale in Internal Reference Mode MX = Reset to Mid-Scale in External Reference Mode Z = Reset to Zero-Scale in Internal Reference Mode FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V H = 4.096V PACKAGE TYPE UD = 16-Lead QFN MSE = 10-Lead MSOP TEMPERATURE GRADE C = Commercial Temperature Range (0C to 70C) I = Industrial Temperature Range (-40C to 85C) H = Automotive Temperature Range (-40C to 125C) PRODUCT PART NUMBER Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2634 PRODUCT SELECTION GUIDE
PART MARKING* PART NUMBER LTC2634-LMI12 LTC2634-LMI10 LTC2634-LMI8 LTC2634-LMX12 LTC2634-LMX10 LTC2634-LMX8 LTC2634-LZ12 LTC2634-LZ10 LTC2634-LZ8 LTC2634-HMI12 LTC2634-HMI10 LTC2634-HMI8 LTC2634-HMX12 LTC2634-HMX10 LTC2634-HMX8 LTC2634-HZ12 LTC2634-HZ10 LTC2634-HZ8 QFN LDQX LDRF LDRN LDQW LDRD LDRM LDQV LDRC LDRK LDRB LDRJ LDRR LDQZ LDRH LDRQ LDQY LDRG LDRP MSOP LTDRV LTDSC LTDSK LTDRT LTDSB LTDSJ LTDRS LTDRZ LTDSH LTDRY LTDSG LTDSP LTDRX LTDSF LTDSN VFS WITH INTERNAL POWER-ON REFERENCE RESET TO CODE 2.5V * (4095/4096) 2.5V * (1023/1024) 2.5V * (255/256) 2.5V * (4095/4096) 2.5V * (1023/1024) 2.5V * (255/256) 2.5V * (4095/4096) 2.5V * (1023/1024) 2.5V * (255/256) 4.096V * (4095/4096) 4.096V * (1023/1024) 4.096V * (255/256) 4.096V * (4095/4096) 4.096V * (1023/1024) 4.096V * (255/256) Mid-Scale Mid-Scale Mid-Scale Mid-Scale Mid-Scale Mid-Scale Zero-Scale Zero-Scale Zero-Scale Mid-Scale Mid-Scale Mid-Scale Mid-Scale Mid-Scale Mid-Scale Zero-Scale Zero-Scale Zero-Scale POWER-ON REFERENCE MODE Internal Internal Internal External External External Internal Internal Internal Internal Internal Internal External External External Internal Internal Internal RESOLUTION 12-Bit 10-Bit 8-Bit 12-Bit 10-Bit 8-Bit 12-Bit 10-Bit 8-Bit 12-Bit 10-Bit 8-Bit 12-Bit 10-Bit 8-Bit 12-Bit 10-Bit 8-Bit VCC 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V MAXIMUM INL 2.5LSB 1LSB 0.5LSB 2.5LSB 1LSB 0.5LSB 2.5LSB 1LSB 0.5LSB 2.5LSB 1LSB 0.5LSB 2.5LSB 1LSB 0.5LSB 2.5LSB 1LSB 0.5LSB
LTDRW 4.096V * (4095/4096) LTDSD 4.096V * (1023/1024) LTDSM 4.096V * (255/256)
*Above options are available in a 16-lead QFN package (LTC2634-UD) or 10-lead MSOP package (LTC2634-MSE).
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LTC2634 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER DC Performance Resolution Monotonicity DNL INL ZSE VOS VOSTC GE GETC Differential Nonlinearity Integral Nonlinearity Zero-Scale Error Offset Error VOS Temperature Coefficient Gain Error Gain Temperature Coefficient VCC = 3V, Internal Ref. (Note 4) VCC = 3V, Internal Ref. (Note 4) VCC = 3V, Internal Ref. (Note 4) VCC = 3V, Internal Ref., Code = 0 VCC = 3V, Internal Ref. (Note 5) VCC = 3V, Internal Ref. VCC = 3V, Internal Ref. VCC = 3V, Internal Ref. (Note 10) C-Grade I-Grade H-Grade Internal Ref., Mid-Scale VCC = 3V 10%, -5mA IOUT 5mA Internal Ref., Mid-Scale VCC = 5V 10%, -10mA IOUT 10mA ROUT DC Output Impedance Internal Ref., Mid-Scale VCC = 3V 10%, -5mA IOUT 5mA Internal Ref., Mid-Scale VCC = 5V 10%, -10mA IOUT 10mA SYMBOL VOUT PSR ISC PARAMETER DAC Output Span Power Supply Rejection Short-Circuit Output Current (Note 6) Sinking Sourcing Positive Supply Voltage Supply Current (Note 7) CONDITIONS External Reference Internal Reference VCC = 3V 10% or 5V 10% VFS = VCC = 5.5V Zero-Scale; VOUT Shorted to VCC Full-Scale; VOUT Shorted to GND For Specified Performance VCC = 3V, VREF = 2.5V, External Reference VCC = 3V, Internal Reference VCC = 5V VREF = 2.5V, External Reference VCC = 5V, Internal Reference
l l l l l l l l l l l l l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2634-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8 (VFS = 2.5V)
CONDITIONS LTC2634-8 LTC2634-10 LTC2634-12 MIN TYP MAX MIN TYP MAX MIN TYP MAX 8 8 0.5 0.05 0.5 0.5 0.5 10 0.2 0.8 10 10 10 0.009 0.016 0.009 0.016 0.09 0.156 0.09 0.156 5 5 0.2 0.5 0.5 10 0.2 0.8 10 10 10 0.035 0.064 0.035 0.064 0.09 0.156 0.09 0.156 MIN TYP 0 to VREF 0 to 2.5 -80 27 -27 2.7 0.5 0.6 0.6 0.7 0.5 0.5 48 -48 5.5 0.7 0.8 0.8 0.9 10 15 10 10 0.5 1 5 5 1 0.5 0.5 10 0.2 0.8 10 10 10 12 12 1 2.5 5 5 UNITS Bits Bits LSB LSB mV mV V/C %FSR ppm/C ppm/C ppm/C
Load Regulation
0.14 0.256 LSB/mA 0.14 0.256 LSB/mA 0.09 0.156 0.09 0.156 MAX UNITS V V dB mA mA V mA mA mA mA A A
Power Supply VCC ICC
ISD
Supply Current in Power-Down Mode (Note 7) VCC = 5V, C-Grade, I-Grade VCC = 5V, H-Grade
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LTC2634 ELECTRICAL CHARACTERISTICS
SYMBOL VREF PARAMETER Input Voltage Range Resistance Capacitance IREF Reference Current, Power-Down Mode Output Voltage Reference Temperature Coefficient Output Impedance Capacitive Load Driving Short-Circuit Current Digital I/O VIH VIL VOH VOL ILK CIN tS Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance Settling Time VCC = 3.6V to 5.5V VCC = 2.7V to 3.6V VCC = 4.5V to 5.5V VCC = 2.7V to 4.5V Load Current = -100A Load Current = 100A VIN = GND to VCC (Note 8) VCC = 3V (Note 9) 0.39% (1LSB at 8 Bits) 0.098% (1LSB at 10 Bits) 0.024% (1LSB at 12 Bits)
l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2634-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8 (VFS = 2.5V)
CONDITIONS
l l l l
MIN 1 120
TYP
MAX VCC
UNITS V k pF A V ppm/C k F mA V V
Reference Input 160 14 DAC Powered Down 0.005 1.24 1.25 10 0.5 10 VCC = 5.5V, REF Shorted to GND 2.4 2.0 0.8 0.6 VCC - 0.4 0.4 1 2.5 2.5 0.1 1.26 200
Reference Output
V V V V A pF
AC Performance 3.3 3.8 4.2 1.0 500 At Mid-Scale Transition 1 DAC Held at FS, 1 DAC Switch 0 - FS External Reference At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference CREF = 0.1F 2.1 2.1 320 180 160 200 180 35 40 680 730 s s s V/s pF nV*s nV*s kHz nV/Hz nV/Hz nV/Hz nV/Hz VP-P VP-P VP-P VP-P
Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse DAC-to-DAC Crosstalk Multiplying Bandwidth en Output Voltage Noise Density
Output Voltage Noise
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LTC2634 ELECTRICAL CHARACTERISTICS
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 PARAMETER SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High CLR Pulse Width LDAC Pulse Width CS/LD High to SCK Positive Edge SCK Frequency CS/LD High to LDAC High or Low Transition SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V 50% Duty Cycle
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2634-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8 (VFS = 2.5V)
CONDITIONS
l l l l l l l l l l l l l l
MIN 4 4 9 9 10 7 7 20 15 7
TYP
MAX
UNITS ns ns ns ns ns ns ns ns ns ns
50 200 20 45
MHz ns ns ns
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LTC2634
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2634-HMI12/-HMI10/-HMI8/-HMX12/-HMX10/-HMX8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V)
SYMBOL PARAMETER DC Performance Resolution Monotonicity DNL INL ZSE VOS VOSTC GE GETC Differential Nonlinearity Integral Nonlinearity Zero-Scale Error Offset Error VOS Temperature Coefficient Gain Error Gain Temperature Coefficient VCC = 5V, Internal Ref. (Note 4) VCC = 5V, Internal Ref. (Note 4) VCC = 5V, Internal Ref. (Note 4) VCC = 5V, Internal Ref., Code = 0 VCC = 5V, Internal Ref. (Note 5) VCC = 5V, Internal Ref. VCC = 5V, Internal Ref. VCC = 5V, Internal Ref. (Note 10) C-Grade I-Grade H-Grade VCC = 5V 10%, Internal Ref., Mid-Scale, -10mA IOUT 10mA VCC = 5V 10%, Internal Ref., Mid-Scale, -10mA IOUT 10mA CONDITIONS External Reference Internal Reference VCC = 5V 10% VFS = VCC = 5.5V Zero-Scale; VOUT Shorted to VCC Full-Scale; VOUT Shorted to GND For Specified Performance VCC = 5V, VREF = 4.096V, External Reference VCC = 5V, Internal Reference VCC = 5V, C-Grade, I-Grade VCC = 5V, H-Grade
l l l l l l l l l l l l l l l l
ELECTRICAL CHARACTERISTICS
CONDITIONS
LTC2634-8 LTC2634-10 LTC2634-12 MIN TYP MAX MIN TYP MAX MIN TYP MAX 8 8 0.5 0.05 0.5 0.5 0.5 10 0.2 0.8 10 10 10 0.006 0.01 0.09 0.156 MIN 5 5 0.2 0.5 0.5 10 0.2 0.8 10 10 10 0.022 0.04 0.09 0.156 TYP 0 to VREF 0 to 4.096 -80 27 -27 4.5 0.6 0.7 0.5 0.5 48 -48 5.5 0.8 0.9 10 15 10 10 0.5 1 5 5 1 0.5 0.5 10 0.2 0.8 10 10 10 12 12 1 2.5 5 5
UNITS Bits Bits LSB LSB mV mV V/C %FSR ppm/C ppm/C ppm/C
Load Regulation ROUT DC Output Impedance
0.09 0.16 LSB/mA 0.09 0.156 MAX UNITS V V dB mA mA V mA mA A A
SYMBOL PARAMETER VOUT PSR ISC DAC Output Span Power Supply Rejection Short-Circuit Output Current (Note 6) Sinking Sourcing Positive Supply Voltage Supply Current (Note 7) Supply Current in Power-Down Mode (Note 7)
Power Supply VCC ICC ISD
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LTC2634
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2634-HMI12/-HMI10/-HMI8/-HMX12/-HMX10/-HMX8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V)
SYMBOL PARAMETER Reference Input VREF Input Voltage Range Resistance Capacitance IREF Reference Current, Power-Down Mode Output Voltage Reference Temperature Coefficient Output Impedance Capacitive Load Driving Short-Circuit Current Digital I/O VIH VIL VOH VOL ILK CIN tS Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance Settling Time Load Current = -100A Load Current = 100A VIN = GND to VCC (Note 8) VCC = 5V (Note 9) 0.39% (1LSB at 8 Bits) 0.098% (1LSB at 10 Bits) 0.024% (1LSB at 12 Bits)
l l l l l l l l l l
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN 1 120
TYP
MAX VCC
UNITS V k pF A V ppm/C k F mA V
160 14 0.005
200 0.1 2.064
DAC Powered Down
Reference Output 2.032 2.048 10 0.5 10 VCC = 5.5V, REF Shorted to GND 2.4 0.8 VCC - 0.4 0.4 1 2.5 4
V V V A pF
AC Performance 3.8 4.2 4.8 1.0 500 At Mid-Scale Transition 1 DAC Held at FS, 1 DAC Switch 0 - FS External Reference At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference CREF = 0.1F 3.0 2.4 320 180 160 250 230 35 50 680 750 s s s V/s pF nV*s nV*s kHz nV/Hz nV/Hz nV/Hz nV/Hz VP-P VP-P VP-P VP-P
Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse DAC-to-DAC Crosstalk Multiplying Bandwidth en Output Voltage Noise Density
Output Voltage Noise
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LTC2634
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2634-HMI12/-HMI10/-HMI8/-HMX12/-HMX10/-HMX8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V)
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 PARAMETER SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High CLR Pulse Width LDAC Pulse Width CS/LD High to SCK Positive Edge SCK Frequency CS/LD High to LDAC High or Low Transition SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF VCC = 4.5V to 5.5V 50% Duty Cycle CONDITIONS
l l l l l l l l l l l l l
ELECTRICAL CHARACTERISTICS
MIN 4 4 9 9 10 7 7 20 15 7
TYP
MAX
UNITS ns ns ns ns ns ns ns ns ns ns
50 200 20
MHz ns ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to GND. Note 3: High temperatures degrade operating lifetimes. Operating lifetime is derated at temperatures greater than 105C. Note 4: Linearity and monotonicity are defined from code kL to code 2N - 1, where N is the resolution and kL is given by kL = 0.016 * (2N/ VFS), rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity is defined from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL = 16 and linearity is defined from code 16 to code 4,095. Note 5: Inferred from measurement at code 16 (LTC2634-12), code 4 (LTC2634-10) or code 1 (LTC2634-8), and at full-scale.
Note 6: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 7: Digital inputs at 0V or VCC. Note 8: Guaranteed by design and not production tested. Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2k in parallel with 100pF to GND. Note 10: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range.
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LTC2634 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, unless otherwise noted. LTC2634-L12 (Internal Reference, VFS = 2.5V) Integral Nonlinearity (INL)
1.0 VCC = 3V 0.5 DNL (LSB) INL (LSB) 0.5 1.0 VCC = 3V
Differential Nonlinearity (DNL)
0
0
-0.5
-0.5
-1.0
0
1024
2048 CODE
3072
4095
2634 G01
-1.0
0
1024
2048 CODE
3072
4095
2634 G02
INL vs Temperature
1.0 VCC = 3V 0.5 INL (LSB) 0.5 DNL (LSB) 1.0
DNL vs Temperature
1.260 VCC = 3V 1.255 DNL (POS) 0 DNL (NEG) -0.5 VREF (V) 1.250
Reference Output Voltage vs Temperature
VCC = 3V
INL (POS)
0
-0.5
INL (NEG)
1.245
-1.0 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
2634 G03
-1.0 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
2634 G04
1.240 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
2634 G05
Settling to 1LSB Rising
CS/LD 5V/DIV
Settling to 1LSB Falling
3/4 SCALE TO 1/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 4.2s
VOUT 1LSB/DIV
3.1s VOUT 1LSB/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2s/DIV
2634 G06
CS/LD 5V/DIV
2s/DIV
2634 G07
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LTC2634 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, unless otherwise noted. LTC2634-H12 (Internal Reference, VFS = 4.096V) Integral Nonlinearity (INL)
1.0 VCC = 5V 0.5 DNL (LSB) INL (LSB) 0.5 1.0 VCC = 5V
Differential Nonlinearity (DNL)
0
0
-0.5
-0.5
-1.0
0
1024
2048 CODE
3072
4095
2634 G08
-1.0
0
1024
2048 CODE
3072
4095
2634 G09
INL vs Temperature
1.0 VCC = 5V INL (POS) DNL (LSB) 1.0
DNL vs Temperature
2.068 VCC = 5V 0.5 DNL (POS) 0 DNL (NEG) -0.5 VREF (V) 2.048 2.058
Reference Output Voltage vs Temperature
VCC = 5V
0.5 INL (LSB)
0 INL (NEG) -0.5
2.038
-1.0 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
2634 G10
-1.0 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
2634 G11
2.028 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
2634 G12
Settling to 1LSB Rising
CS/LD 5V/DIV
Settling to 1LSB Falling
1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 4.8s
VOUT 1LSB/DIV
3.8s 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2s/DIV
2634 G13
VOUT 1LSB/DIV
CS/LD 5V/DIV
2s/DIV
2634 G14
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LTC2634 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, unless otherwise noted
LTC2634-10 Integral Nonlinearity (INL)
1.0 VCC = 3V VFS = 2.5V INTERNAL REF 0.5 DNL (LSB) INL (LSB) 0.5 1.0
Differential Nonlinearity (DNL)
VCC = 3V VFS = 2.5V INTERNAL REF
0
0
-0.5
-0.5
-1.0
0
256
512 CODE
768
1023
2634 G15
-1.0
0
256
512 CODE
768
1023
2634 G16
LTC2634-8 Integral Nonlinearity (INL)
0.50 VCC = 3V VFS = 2.5V INTERNAL REF 0.50
Differential Nonlinearity (DNL)
VCC = 3V VFS = 2.5V INTERNAL REF
0.25 DNL (LSB) 0 64 128 CODE 192 255
2634 G17
0.25
INL (LSB)
0
0
-0.25
-0.25
-0.50
-0.50
0
64
128 CODE
192
255
2634 G18
LTC2634 Load Regulation
10 8 6 4 VOUT (mV) VOUT (V) 2 0 -2 -4 -6 -8 -10 -30 -20 -10 INTERNAL REF. CODE = MID-SCALE 0 10 IOUT (mA) 20 30
2634 G19
Current Limiting
0.20 3 VCC = 5V (LTC2634-H) VCC = 5V (LTC2634-L) VCC = 3V (LTC2634-L) OFFSET ERROR (mV) INTERNAL REF. CODE = MID-SCALE -20 -10 0 10 IOUT (mA) 20 30
2634 G20
Offset Error vs Temperature
VCC = 5V (LTC2634-H) VCC = 5V (LTC2634-L) VCC = 3V (LTC2634-L)
0.15 0.10 0.05 0 -0.05 -0.01 -0.15
2 1 0 -1 -2 -3 -50 -25
-0.20 -30
0
25 50 75 100 125 150 TEMPERATURE (C)
2634 G21
2634f
13
LTC2634 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, unless otherwise noted
LTC2634 Large-Signal Response Mid-Scale Glitch Impulse Power-On Reset Glitch
LTC2634-L
CS/LD 5V/DIV VOUT 0.5V/DIV VOUT 5mV/DIV VFS = VCC = 5V 1/4 SCALE to 3/4 SCALE 2s/DIV
2634 G22
VCC 2V/DIV LTC2634-H12, VCC = 5V 3.0nV*s TYP VOUT 5mV/DIV LTC2634-L12, VCC = 3V 2.1nV*s TYP 2s/DIV
2634 G23
ZERO SCALE
200s/DIV
2636 G24
Headroom at Rails vs Output Current
5.0 4.5 4.0 3.5 VOUT (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5V SINKING 3V (LTC2634-L) SINKING 1 2 3 456 IOUT (mA) 7 8 9 10 VOUT 0.5V/DIV 3V (LTC2634-L) SOURCING CS/LD 2V/DIV 5V SOURCING
Exiting Power-Down to Mid-Scale
LTC2634-H VCC = 5V INTERNAL REF VCC 2V/DIV
Power-On Reset to Mid-Scale
LTC2634-H
DACs A-C IN POWER-DOWN MODE VOUT 0.5V/DIV LTC2634-L
5s/DIV
2634 G26
200s/DIV
2634 G27
2634 G25
Supply Current vs Logic Voltage
1.4 SWEEP SCK, SDI, CS/LD BETWEEN 0V AND VCC VOUT 1V/DIV ICC (mA) 1.0 VCC = 5V 0.8 VCC = 3V (LTC2634-L) CLR 5V/DIV
Hardware CLR
VCC = 5V VREF = 4.096V CODE = FULL-SCALE VOUT 1V/DIV
Hardware CLR to Mid-Scale
VCC = 5V VREF = 4.096V CODE = FULL-SCALE
1.2
0.6
CLR 5V/DIV
0.4
0
1
3 2 LOGIC VOLTAGE (V)
4
5
2634 G28
1s/DIV
2634 G29
1s/DIV
2634 G30
2634f
14
LTC2634 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, unless otherwise noted
LTC2634 Mulitplying Bandwidth
2 0 NOISE VOLTAGE (nV/Hz) -2 -4 -6 dB -8 -10 -12 -14 -16 -18 1k VCC = 5V VREF(DC) = 2V VREF(AC) = 0.2VP-P CODE = FULL-SCALE 10k 100k FREQUENCY (Hz) 1M
2636 G31
Noise Voltage vs Frequency
500 VCC = 5V CODE = MID-SCALE INTERNAL REF GAIN ERROR (%FSR) 1.0
Gain Error vs Reference Input
VCC = 5.5V 0.8 GAIN ERROR OF 4 CHANNELS 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
400
300 LTC2634-H 200 LTC2634-L 100
0 100
-1.0 1k 10k 100k FREQUENCY (Hz) 1M
2636 G32
1
1.5
2 2.5 3 3.5 4 4.5 REFERENCE VOLTAGE (V)
5
5.5
2634 G33
0.1Hz to 10Hz Voltage Noise
VCC = 5V, VFS = 2.5V CODE = MID-SCALE INTERNAL REF
DAC-to-DAC Crosstalk (Dynamic)
1.0
Gain Error vs Temperature
10V/DIV
1 DAC SWITCH 0-FS 2V/DIV VOUT 1mV/DIV
GAIN ERROR (%FSR) LTC2634-H12, VCC = 5V 2.4nV*s TYP CREF = 0.1F 2s/DIV
2634 G35
CS/LD 5V/DIV
0.5
0
-0.5
1s/DIV
2634 G34
-1.0 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
2634 G36
2634f
15
LTC2634 PIN FUNCTIONS
(QFN/MSOP)
VOUTA to VOUTD (Pins 1-2, 11-12/Pins 2-3, 8-9): DAC Analog Voltage Outputs. LDAC (Pin 3, QFN Only): Asynchronous DAC Update Pin. If CS/LD is high, a falling edge on LDAC immediately updates the DAC registers with the contents of the input registers (similar to a software update). If CS/LD is low when LDAC goes low, the DAC registers are updated after CS/LD returns high. A low on the LDAC pin powers up the DACs. A software power-down command is ignored if LDAC is low. CS/LD (Pin 4/Pin 4): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the 32-bit shift register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. SCK (Pin 5/Pin 5): Serial Interface Clock Input. CMOS and TTL compatible. NC (Pins 6, 15, QFN Only): No Connect. Not internally connected. SDO (Pin 7, QFN Only): Serial Interface Data Output. The serial output of the 32-bit shift register appears at the SDO pin. The data transferred to the device via the SDI pin is delayed 32 SCK rising edges before being output at the next falling edge. This pin is used for daisy-chain operation, it is always driven and never goes high impedance, even when CS/LD is high. See the Daisy-Chain Operation section.
SDI (Pin 8/Pin 6): Serial Interface Data Input. Data on SDI is clocked into the DAC on the rising edge of SCK. The LTC2634 accepts input word lengths of either 24 or 32 bits. CLR (Pin 9, QFN Only): Asynchronous Clear Input. A logic low at this level-triggered input clears all registers and causes the DAC voltage output to reset to zero (LTC2634-Z) or mid-scale (LTC2634-MI/-MX). CMOS and TTL compatible. REF (Pin 10/Pin 7): Reference Voltage Input or Output. When external reference mode is selected, REF is an input (1V VREF VCC) where the voltage supplied sets the full-scale DAC output voltage. When internal reference is selected, the 10ppm/C 1.25V (LTC2634-L) or 2.048V (LTC2634-H) internal reference (half full-scale) is available at REF This output may be bypassed to GND with up . to 10F and must be buffered when driving external DC load current. REFLO (Pin 13, QFN only): Reference Low Pin. The voltage at this pin sets the zero-scale voltage of all DACs. This pin must be tied to GND. GND (Pin 14/Pin 10): Ground. VCC (Pin 16/Pin 1): Supply Voltage Input. 2.7V VCC 5.5V (LTC2634-L) or 4.5V VCC 5.5V (LTC2634-H). Bypass to GND with a 0.1F capacitor. Exposed Pad (Pin 17/Pin 11): Ground. Must be soldered to PCB ground.
2634f
16
LTC2634 BLOCK DIAGRAM
GND INTERNAL REFERENCE SWITCH VREF (REFLO) REGISTER REGISTER REGISTER VOUTA REGISTER VCC VOUTD REF
DAC A
DAC D
VREF REGISTER REGISTER REGISTER VOUTB REGISTER DAC B DAC C
VREF VOUTC
CS/LD CONTROL LOGIC DECODE
SDI
SDI
SCK (LDAC) ( ) QFN PACKAGE ONLY
32-BIT SHIFT REGISTER
POWER-ON RESET
(CLR) (SDO)
2634 BD
TIMING DIAGRAMS
t1 t2 SCK 1 t3 2 t4 3 23 t6 24 t10 SDI t5 CS/LD t12 SDO t11 LDAC
2634 F01a
t7
t9
Figure 1a
CS/LD t11 LDAC
2634 F01b
Figure 1b
2634f
17
LTC2634 OPERATION
The LTC2634 is a family of quad voltage output DACs in 16-lead QFN and 10-lead MSOP packages. Each DAC can operate rail-to-rail using an external reference, or with its full-scale voltage set by an integrated reference. Eighteen combinations of accuracy (12-, 10- and 8-bit), power-on reset value (zero-scale, mid-scale in internal reference mode, or mid-scale in external reference mode), and fullscale voltage (2.5V or 4.096V) are available. The LTC2634 is controlled using a 3-wire SPI/MICROWIRE compatible interface. Power-On Reset The LTC2634-HZ/LTC2634-LZ clear the output to zero-scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2634 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 5mV above zeroscale during power on. In general, the glitch amplitude decreases as the power supply ramp time is increased. See "Power-On Reset Glitch" in the Typical Performance Characteristics section. The LTC2634-HMI/LTC2634-HMX/LTC2634-LMI/ LTC2634-LMX provide an alternative reset, setting the output to mid-scale when power is first applied. The LTC2634-LMI and LTC2634-HMI power up in internal reference mode, with the output set to a mid-scale voltage of 1.25V and 2.048V, respectively. The LTC2634-LMX and LTC2634-HMX power up in external reference mode, with the output set to mid-scale of the external reference. Default reference mode selection is described in the Reference Modes section. Power Supply Sequencing The voltage at REF (Pin 10, QFN/Pin 7, MSOP) must be kept within the range -0.3V VREF VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turnon and turn-off sequences, when the voltage at VCC is in transition. Transfer Function The digital-to-analog transfer function is: k VOUT(IDEAL) = N ( VREF - VREFLO ) + VREFLO 2 where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is either 2.5V (LTC2634-LMI/LTC2634-LMX/LTC2634-LZ) or 4.096V (LTC2634-HMI/LTC2634-HMX/LTC2634-HZ) when in internal reference mode, and the voltage at REF when in external reference mode. The resulting DAC output span is 0V to VREF , as it is necessary to tie REFLO to GND. Serial Interface The CS/LD input is level-triggered. When this input is taken low, it acts as a chip-select signal, enabling the SDI and SCK buffers and the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first; then the 4-bit DAC address, A3-A0; and finally the 16-bit data word. The data word comprises the 12-, 10- or 8-bit input code, ordered MSB to LSB, followed by 4, 6 or 8 don't-care bits (LTC2634-12/LTC2634-10/LTC2634-8 respectively; see Figure 2). Data can only be transferred to the device when the CS/LD signal is low, beginning on the first rising edge of SCK. SCK may be high or low at the falling edge
2634f
18
LTC2634 OPERATION
of CS/LD. The rising edge of CS/LD ends the data transfer and causes the device to execute the command specified in the 24-bit input sequence. The complete sequence is shown in Figure 3a. The command (C3-C0) and address (A3-A0) assignments are shown in Tables 1 and 2. The first four commands in Table 1 consist of write and update operation. A write operation loads a 16-bit data word from the 24-bit shift register into the input register of the selected DAC, n. An
Input Word (LTC2634-12)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 D11 D10 D9 MSB D8 DATA (12 BITS + 4 DON'T CARE BITS) D7 D6 D5 D4 D3 D2 D1 D0 LSB X X X X
update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 12-, 10- or 8-bit input code, and is converted to an analog voltage at the DAC output. Write to and update combines the first two commands. The update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram.
Input Word (LTC2634-10)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 D9 MSB D8 D7 D6 DATA (10 BITS + 6 DON'T CARE BITS) D5 D4 D3 D2 D1 D0 LSB X X X X X X
Input Word (LTC2634-8)
COMMAND C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 D7 MSB D6 D5 D4 DATA (8 BITS + 8 DON'T CARE BITS) D3 D2 D1 D0 LSB X X X X X X X X
2634 F02
Figure 2. Command and Data Input Format Table 1. Command Codes
COMMAND* C3 0 0 0 0 0 0 0 0 1 C2 0 0 0 0 1 1 1 1 1 C1 0 0 1 1 0 0 1 1 1 C0 0 1 0 1 0 1 0 1 1 Write to Input Register n Update (Power Up) DAC Register n Write to Input Register n, Update (Power Up) All Write to and Update (Power Up) DAC Register n Power-Down DAC n Power-Down Chip (All DACs and Reference) Select Internal Reference (Power-Up Reference) Select External Reference (Power-Down Internal Reference) No Operation
2634f
Table 2. Address Codes
ADDRESS (n)* A3 0 0 0 0 1 A2 0 0 0 0 1 A1 0 0 1 1 1 A0 0 1 0 1 1 DAC A DAC B DAC C DAC D All DACs
* Address codes not shown are reserved and should not be used.
*Command codes not shown are reserved and should not be used.
19
LTC2634 OPERATION
While the minimum input sequence is 24 bits, it may optionally be extended to 32 bits to accommodate microprocessors that have a minimum word width of 16 bits (2 bytes). To use the 32-bit width, 8 don't care bits must be transferred to the device first, followed by the 24-bit sequence described. Figure 3b shows the 32-bit sequence. The 16-bit data word is ignored for all commands that do not include a write operation. Daisy-Chain Operation (QFN Package) The serial output of the shift register appears at the SDO pin on the QFN package. Data transferred to the device from the SDI input is delayed 32 SCK rising edges before being output at the next SCK falling edge, therefore, daisy chaining multiple LTC2634 DACs requires 32-bit data write cycles. The SDO output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., SCK, SDI and CS/LD). Such a "daisy-chain" series is configured by connecting SDO of each upstream device to SDI of the next device in the chain. The shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. Because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the first instruction addresses the last device in the chain and so forth. The SCK and CS/LD signals are common to all devices in the series. Figure 5 shows a block diagram for daisy-chain operation. In use, CS/LD is first taken low. Then the concatenated input data is transferred to the chain, using SDI of the first device as the data input. When the data transfer is complete, CS/LD is taken high, completing the instruction sequence for all devices simultaneously. A single device can be controlled by using the no-operation command (1111) for the other devices in the chain. Reference Modes For applications where an accurate external reference is either not available, or not desirable due to limited space, the LTC2634 has a low noise, user-selectable, integrated reference. The integrated reference voltage is internally amplified by 2x to provide the full-scale DAC output voltage range. The LTC2634-LMI/LTC2634-LMX/LTC2634-LZ provides a full-scale DAC output of 2.5V. The LTC2634HMI/LTC2634-HMX/LTC2634-HZ provides a full-scale DAC output of 4.096V. The internal reference can be useful in applications where the supply voltage is poorly regulated. Internal Reference mode can be selected by using command 0110b, and is the power-on default for LTC2634-HZ/LTC2634-LZ, as well as for LTC2634-HMI/ LTC2634-LMI. The 10ppm/C, 1.25V (LTC2634-LMI/LTC2634-LMX/ LTC2634-LZ) or 2.048V (LTC2634-HMI/LTC2634-HMX/ LTC2634-HZ) internal reference is available at the REF pin. Adding bypass capacitance to the REF pin will improve noise performance; 0.1F is recommended, and up to 10F can be driven without oscillation. The REF output must be buffered when driving an external DC load current. Alternatively, the DAC can operate in external reference mode using command 0111b. In this mode, an input voltage supplied externally to the REF pin provides the reference (1V VREF VCC) and the supply current is reduced. The external reference voltage supplied sets the full-scale DAC output voltage. External reference mode is the power-on default for LTC2634-HMX/LTC2634-LMX. The reference mode of LTC2634-HZ/LTC2634-LZ/ LTC2634-HMI/LTC2634-LMI (internal reference power-on default), can be changed by software command after power up. The same is true for LTC2634-HMX/-LMX (external reference power-on default). The LTC2634's QFN package offers a REFLO pin for the negative reference. REFLO must be connected to GND.
2634f
20
LTC2634 OPERATION
Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than four DAC outputs are needed. When in power down, the buffer amplifiers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. The DAC outputs are put into a high impedance state, and the output pins are passively pulled to ground through individual 200k resistors. Input- and DAC-register contents are not disturbed during power down. Any DAC channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The supply current is reduced approximately 20% for each DAC powered down. The integrated reference is automatically powered down when external reference is selected using command 0111b. In addition, all the DAC channels and the integrated reference together can be put into powerdown mode using power-down chip command 0101b. When the integrated reference and all DAC channels are in power-down mode, the REF pin becomes high impedance (typically > 1G). For all power-down commands the 16-bit data word is ignored. Normal operation resumes after executing any command that includes a DAC update, (as shown in Table 1) or pulling the asynchronous LDAC pin low. The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than four DACs are in a powered-down state prior to the update command, the power-up delay time is 10s. However, if all four DACs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the DAC amplifiers and reference buffers. In this case, the power-up delay time is 12s. The power-up of the integrated reference depends on the command that powered it down. If the reference is powered down using the select external reference command (0111b), then it can only be powered back up using select internal reference command (0110b). However, if the reference was powered down using power-down chip command (0101b), then in addition to select internal reference command (0110b), any command (in software or using the LDAC pin) that powers up the DACs will also power up the integrated reference. Voltage Output The LTC2634's integrated rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to 10mA at 5V, and 5mA at 3V. Load regulation is a measure of the amplifier's ability to maintain the rated voltage accuracy over a wide range of load current. The measured change in output voltage per change in forced load current is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to ohms. The amplifier's DC output impedance is 0.1 when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50 typical channel resistance of the output devices (e.g., when sinking 1mA, the minimum output voltage is 50 * 1mA, or 50mV). See the graph "Headroom at Rails vs Output Current" in the Typical Performance Characteristics section. The amplifier is stable driving capacitive loads of up to 500pF .
2634f
21
LTC2634 OPERATION
Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog output of the DAC cannot go below ground, it may limit for the lowest codes as shown in Figure 4b. Similarly, limiting can occur near full-scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC, as shown in Figure 4c. No full-scale limiting can occur if VREF is less than VCC - FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. Board Layout The PC board should have separate areas for the analog and digital sections of the circuit. A single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. The resistance from the LTC2634 GND pin to the ground plane should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.1). Note that the LTC2634 is no more susceptible to this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Another technique for minimizing errors is to use a separate power ground return trace on another board layer. The trace should run between the point where the power supply is connected to the board and the DAC ground pin. Thus the DAC ground pin becomes the common point for analog ground, digital ground, and power ground. When the LTC2634 is sinking large currents, this current flows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. It is sometimes necessary to interrupt the ground plane to confine digital ground currents to the digital portion of the plane. When doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap.
2634f
22
CS/LD 1 2 7 14 17 D3
2634 F03a
SCK 3 4 10 13 D7 DATA WORD D6 D5 D4 D2 D1 D0 X X X X 21 23 D10 D9 D8 11 12 18 24 22 16 20 C0 ADDRESS A3 A2 A1 A0 D11 5 6 8 9 19 15 C1 C2 COMMAND WORD
OPERATION
SDI
C3
24-BIT INPUT WORD
Figure 3a. LTC2634-12 24-Bit Load Sequence (Minimum Input Word) LTC2634-10 SDI Data Word: 10-Bit Input Code + 6 Don't Care Bits LTC2634-8 SDI Data Word: 8-Bit Input Code + 8 Don't Care Bits
CS/LD 6 7 14 17 D11 D10 D9 D8 D7 D6 A2 ADDRESS WORD C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 A1 A0 X COMMAND WORD X X X C3 C2 C1 X C3 C2 C1 C0 A3 8 9 10 13 11 12 21 16 18 20 22 15 19 X 23 D5 24 D4 25 D3 DATA WORD D4 D3 D2 D1 D0 X X X X 26 D2 27 D1 28 D0 29 X 30 X 31 X 32 X
SCK
1
2
3
4
5
SDI
X
X
X
X
X
DON'T CARE
SDO
X
X
X
X
X
PREVIOUS 32-BIT INPUT WORD t1 t2 SCK SDI SDO 17 t3 D11 t12 PREVIOUS D11 PREVIOUS D10 t4 D10 18
CURRENT 32-BIT INPUT WORD
2634 F03b
Figure 3b. LTC2634-12 32-Bit Load Sequence (Required for Daisy-Chain Operation) LTC2634-10 SDI Data Word: 10-Bit Input Code + 6 Don't Care Bits LTC2634-8 SDI Data Word: 8-Bit Input Code + 8 Don't Care Bits
LTC2634
23
2634f
LTC2634 OPERATION
VREF = VCC POSITIVE FSE
VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE OUTPUT VOLTAGE 0V 0 2,048 INPUT CODE 4,095
2634 F04
(4c)
0V NEGATIVE OFFSET INPUT CODE
(4a) (4b)
Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown in 12 Bits) (4a) Overall Transfer Function (4b) Effect of Negative Offset for Codes Near Zero (4c) Effect of Postitive Full-Scale Error for Codes Near Full-Scale
SCK CS/LD 4 CS/LD 5 SCK 6 SDI 4 CS/LD 5 SCK 6 SDI 4 CS/LD 5 SCK 6 SDI
LTC2634UD SDO 7
LTC2634UD SDO 7
LTC2634UD SDO 7 DATA OUTPUT
SDI
***
2634 F05
Figure 5. Daisy-Chain Operation (QFN Only)
2634f
24
LTC2634 DACs Adjusts LTC2755-16 Offsets, Amplified with LT1991 PGA to 5V
TYPICAL APPLICATION
15V VDD LTC2755 RFBA 60 0.1F IOUT1A 59 DAC A IOUT2A 2 1/2 LT1469 RVOSA 58 4 7 0.1F -15V 2 DAC A DAC D 0.1F REF LTC2634MSE-LMI12 9 VCC 1 0.1F 1k 1 OUTA 2 8 2k 5V 15V
5V
15
0.1F
0.1F
8
+
3
5
61 ROFSA
64 RIN1
1/2 LT1469
0.1F
-15V
62 REFA
DAC D 30k 3 DAC B CS/LD SCK SDI GND 10 4 OUTB 6 -15V 30k SERIAL BUS 5 -15V DAC C 8
30k GND
19
-15V
2634 TA02
+ -
+ -
OUTC DAC C DAC B
+
4
-
6
63 RCOM1
-
7
15V 0.1F
0.1F 8 7 M9 9 M3 VCC 10 M1 6 OUT LT1991 1 REF P1 2 P3 VEE 5 3 4 P9 0.1F -15V
VOUT 5V
LTC2634
25
2634f
LTC2634 PACKAGE DESCRIPTION
UD Package 16-Lead Plastic QFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 0.05
3.50
0.05 2.10
1.45 0.05 0.05 (4 SIDES)
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 0.05 BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 15 16 0.40 1 1.45 0.10 (4-SIDES) 2 0.10 PIN 1 NOTCH R = 0.20 TYP OR 0.25 45 CHAMFER
3.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6)
(UD16) QFN 0904
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25
0.05
0.50 BSC
2634f
26
LTC2634 PACKAGE DESCRIPTION
MSE Package 10-Lead Plastic MSOP Exposed Die Pad ,
(Reference LTC DWG # 05-08-1664 Rev C)
BOTTOM VIEW OF EXPOSED PAD OPTION
2.794 (.110
0.102 .004)
0.889 (.035
0.127 .005)
1
2.06 0.102 (.081 .004) 1.83 0.102 (.072 .004)
0.29 REF
5.23 (.206) MIN
2.083 (.082
0.102 3.20 - 3.45 .004) (.126 - .136)
0.05 REF DETAIL "B" CORNER TAIL IS PART OF DETAIL "B" THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 0.497 0.076 (.0196 .003) REF
10
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6
4.90 0.152 (.193 .006) 0.254 (.010) GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 1.10 (.043) MAX DETAIL "A" 0 - 6 TYP 12345
3.00 0.102 (.118 .004) (NOTE 4)
0.86 (.034) REF
0.17 - 0.27 (.007 - .011) TYP
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.50 (.0197) BSC
0.1016 (.004
0.0508 .002)
MSOP (MSE) 0908 REV C
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2634 RELATED PARTS
PART NUMBER LTC1660/LTC1665 LTC1663 LTC1664 LTC1669 LTC1821 LTC2600/LTC2610/ LTC2620 LTC2601/LTC2611/ LTC2621 LTC2602/LTC2612/ LTC2622 LTC2604/LTC2614/ LTC2624 LTC2605/LTC2615/ LTC2625 LTC2606/LTC2616/ LTC2626 LTC2609/LTC2619/ LTC2629 LTC2630 LTC2631 LTC2636 LTC2640 DESCRIPTION Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP Single 10-Bit VOUT DAC in SOT-23 Quad 10-Bit VOUT DAC in 16-Pin Narrow SSOP Single 10-Bit VOUT DAC in SOT-23 Parallel 16-Bit Voltage Output DAC Octal 16-/14-/12-Bit VOUT DACs in 16-Lead Narrow SSOP Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP Octal 16-/14-/12-Bit VOUT DACs with I2C Interface Single 16-/14-/12-Bit VOUT DACs with I2C Interface Quad 16-/14-/12-Bit VOUT DACs with I2C Interface Single 12-/10-/8-Bit VOUT DACs with 10pmm/C Reference in SC70 Single 12-/10-/8-Bit I2C VOUT DACs with 10pmm/C Reference in ThinSOTTM Octal 12-/10-/8-Bit VOUT DACs with 10pmm/C Reference Single 12-/10-/8-Bit VOUT DACs with 10pmm/C Reference in ThinSOT COMMENTS VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output VCC = 2.7V to 5.5V, 60A, Internal Reference, SMBus Interface VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output VCC = 2.7V to 5.5V, 60A, Internal reference, I2C Interface Precision 16-Bit Settling in 2s for 10V Step 250A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 300A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 300A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 250A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 250A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, I2C Interface 270A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, I2C Interface 250A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with Separate VREF Pins for Each DAC 180A per DAC, 2.7V to 5.5V Supply Range, 10pmm/C Reference, Rail-to-Rail Output, SPI Serial Interface 180A per DAC, 2.7V to 5.5V Supply Range, 10pmm/C Reference, External REF Mode, Rail-to-Rail Output, I2C Interface 125A per DAC, 2.7V to 5.5V Supply Range, 10pmm/C Reference, External REF Mode, Rail-to-Rail Output, SPI Interface 180A per DAC, 2.7V to 5.5V Supply Range, 10pmm/C Reference, External REF Mode, Rail-to-Rail Output, SPI Interface
ThinSOT is a trademark of Linear Technology Corporation
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28 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0309 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2009

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